1Gb NAND + 512Mb LPDDR2

• Features

  W29N01GZ NAND Flash Memory
  • Basic Features
  – Density : 1Gbit (Single chip solution)
  – Vcc : 1.7V to 1.95V
  – Bus width : x8
  – Operating temperature
     Industrial: - 40°C to 85°C
  • Single-Level Cell (SLC) technology.
  • Organization
  – Density: 1G-bit/128M-byte
  – Page size:1,056 words(1024 +32 words)
  – Block size:64 pages(64K +2K words)
  • Highest Performance
  – Read performance (Max.)
     Random read: 25us
     Sequential read cycle: 35ns
  – Write Erase performance
     Page program time: 300us(typ.)
     Block erase time: 2ms(typ.)
  – Endurance 100K Erase/Program Cycles
  – 10-years data retention
  • Command set
  – Standard NAND command set
  – Additional command support
     Sequential Cache Read
     Random Cache Read
     Cache Program
     Copy Back
     OTP Data Program, Data Lock by Page and Data Read
  • Lowest power consumption
  – Read: 10mA(typ.)
  – Program/Erase: 10mA(typ.)
  – CMOS standby: 10uA(typ.)

  W979H2KK Low Power DDR2 SDRAM
  • VDD1 = 1.7~1.95V
  • VDD2/VDDCA/VDDQ = 1.14V~1.30V
  • Data width: x32
  • Clock rate: up to 400 MHz2
  • Data rate: up to 800 Mb/s/pad2
  • Four-bit pre-fetch DDR architecture
  • Four internal banks
  • Programmable READ and WRITE latencies (RL/WL)
  • Programmable burst lengths: 4, 8, or 16
  • Auto refresh: All bank refresh mode only
  • Partial Array Self-Refresh (PASR):
  • All bank or per bank, bank mask is supported but segment mask is not supported
  • Pre-charge command: All bank or per bank
  • Read with auto-pre-charge
  • Write with auto-pre-charge
  • Deep Power Down Mode (DPD Mode)
  • Programmable output buffer driver strength
  • Data mask (DM) for write data
  • Clock Stop capability during idle periods
  • Double data rate for data output
  • Differential clock inputs
  • Bidirectional differential data strobe
  • Interface: HSUL_12
  • JEDEC LPDDR2-S4B compliance
  • Operating Temperature Range:
  -40°C ≤ Tj ≤ 85°C

Package

8x10.5x1.0