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The W972GG8KS is a 2G bits DDR2 SDRAM, and speed involving -18, -25/25I and -3.



Density 2Gb Status Mass Production
Vcc 1.8V±0.1V Frequency 333 / 400 / 533 MHz
Package WBGA 60 Tempture Range C-temp, I-temp, Automotive
Feature List Double Data Rate architecture: two data transfers per clock cycle

CAS Latency: 3, 4, 5, 6 and 7

Burst Length: 4 and 8

Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data

Edge-aligned with Read data and center-aligned with Write data

DLL aligns DQ and DQS transitions with clock

Differential clock inputs (CLK and /CLK)

Data masks (DM) for write data

Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS

Posted /CAS programmable additive latency supported to make command and data bus efficiency

Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality

Auto-precharge operation for read and write bursts

Auto Refresh and Self Refresh modes

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = Read Latency - 1 (WL = RL - 1)

Interface: SSTL_18
Datasheet Buy Online

Technical Documentation

Resources

Product Brief

Specialty DRAM and Mobile DRAM

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  • File Type:pdf
  • Updated:27/05/2020
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