Top Questions
Code Storage Flash Memory
What are the differences between Continuous Read mode and Sequential Read mode of QSPI NAND Flash?

The Continuous Read mode can support Flash internal ECC with ECC-E bit=1, but Sequential Read mode cannot, it needs SoC to do ECC.  In addition, the Data Output Structure in Continuous Read mode does not include spare area.

What are the rules of layout about flash on PCB?

The basic rules for Flash memory are to keep the decoupling capacitor as near as possible to the chip VCC/GND pins, and there should have large VCC/ground plane under the chip.

What are the reasons of unstable reading of SPI NOR flash?

Unstable reading is only a symptom. Possible reasons include unstable or insufficient voltage during programing, unexpected power loss during erasing, or the flash cell may already be damaged which requires FA analysis to determine the root cause.

What is the difference between serial flash suffix Q/N/M

1. The difference between suffix N and Q: output drive strength of Q suffix flash is 25% or 50%, output drive strength of N suffix flash is 75%.

2. The difference between the suffix M and Q: default QE bit of M suffix flash is 0 and can be modified to 1; QE bit of Q suffix flash is fix to 1. M suffix flash has QPI/DTR/continuous read mode functions, but Q suffix flash does not have those features.

How to protect serial NOR Flash data?

1. To protect different areas, the SEC/TB/BP[2:0] bits in Status Register 1 and the CMP bit in Status Register 2 are configured according to the memory protection table in the datasheet when the WPS bit in Status Register 3 is set to 0 (the default value). These protected areas cannot be erased or programmed.

2. Setting the WPS bit to 1 (WPS=1) in Status Register 3 activates individual block memory protection. Protection is configured according to the corresponding sector and block settings in the datasheet. Data in these protected areas of Flash cannot be erased or programmed. In this mode(WPS=1), the original settings of Status Register 1 are automatically overridden.

Does serial NOR flash support OTP?


1. Support 3x256-Bytes Security Registers with OTP locks. The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP) bits, once it is set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

2. After setting the OTP area of the Main Array as desired based on the BP bits protection table, setting the SRL bit of SR2 to 1 according to a special sequence creates the OTP area by permanently locking the Status registers. Please contact Winbond for details regarding the special instruction sequence (AN0000003 Special One Time Program for SPI flash).

What is the difference between Serial NOR’s JV series and RV series?

They are the same technology, but some performances are improved. Please refer the migration guide. 

The W25Q64JVSSIQ data sheet does not specify any specifications regarding turning the power back on after the power is turned off, but are there any restrictions such as "VCC must be kept below yyV for xx seconds"?

VCC must be kept below 0.8V for at least 100us.

(The above specifications are not listed in the industrial grade datasheet of the JV/JW series, but are listed in the automotive grade.)

Is an internal pull-up resistor mounted on the /RESET pin of W25R256JV? The W25Q256JV datasheet states that the /RESET pin has an internal pull-up resistor, but the W25R256JV datasheet does not have such description.

Yes, the /RESET pin of W25R256JV also has an internal pull-up resistor.

The Serial NAND W25N0xKx series does not have Bad Block Management, but how should user handle Initial Bad Blocks when reading multiple blocks continuously using Sequential Read?

W25N0xKx is not equipped with Bad Block Management, so even if the Initial Bad Block is included within the read address range, data from the Initial Bad Block will be read. Therefore, processing is required on the SoC side to exclude data read from the Initial Bad Block.

What advantages does Sequential Read mode offer, and in what scenarios should it be utilized?

Sequential Read mode allows users to implement bit error correction when facilitated by an external ECC engine. It enables access to the entire memory array both the Main Area and the Spare Area, with a single Read command. This is ideal for code shadowing applications.

What are the spec differences between the suffixes of SPI NAND products?

The suffix characters indicate the default operation of the Read Mode. The suffix U signifies Sequential Read mode, while C and T denote Continuous Read mode. The other suffixes (R, E, F, and G) default to Buffer Read mode.

Can I read the SPI NOR flash while it is executing Block Erase (64KB)?

This operation is usually not recommended. Please note, during Block erase the Read command will be ignored and only Read Status Register or S/W Reset commands will be accepted. If the user wants to read or write the other blocks of the flash memory array during a Block erase, the Erase suspend command can be used to do read or write operation.

For SPI NOR Flash, Winbond data sheet defines the clock high tCLH and clock low tCLL timing have to be greater than 45%Pc, Pc=1/fc(max). What does 45% Pc mean?

The 45% Pc here means the minimum CLK period calculated based on the maximum CLK frequency. The following calculation uses 133MHz CLK freq as an example and the min. calculated timing is 45% * 1/133MHz=45% * 7.5ns=3.375ns, so as long as tCLH and tCLL ≥ 3.375ns, there is no problem.

Do we need to add the 66h/99h Reset command during Power on for SPI NOR flash?

Actually, it depends on the actual situation. For example, if the VCC is not dropped to the VPWD level and pulled up again during actual application, it may cause a flash exception. At this time, a reset is needed to recover it. 66h/99h is very useful, so it is recommended to add the 66h/99h Soft Reset command after power on.

How to enable reset pin function of SPI NOR flash with SOP8 package?

Please select W25QXXXXM part and change S23 bit of Status Register-3 from 0 to 1. S23 bit in status register-3 is called HOLD/RST bit, when HOLD/RST=0 (factory default), the pin acts as /HOLD; when HOLD/RST=1, the pin acts as /RESET.

What is the difference between QSPI and QPI?

QSPI requires a single input for commands only, and addresses/data go in and out through 4 inputs and outputs. QPI is always 4 inputs and outputs for command, address and data. (QPI: Quad Peripheral Interface)

If the Quad Enable bit (QE) is set to 1, the /WP and /Hold or /RESET pins become IO2 and IO3. In this case, does it mean /WP and /Hold or /RESET functions cannot be used?

The function of the /Hold or /RESET pin has been disabled and can no longer be used when QE bit is set to 1, but the function of the /WP pin operates in single SPI mode, so it can still be used.

Are external 10K ohm pull up resistors required on the CS_L, WP_L/IO2, and HOLD_L/IO3 pins when using Winbond Flash memory products?

The pull up resistor for /CS pin is highly recommended and the typical value is 10K ohm. For IO2 and IO3 pins in Quad SPI mode, pull-up resistors are optional if BOM cost saving is critical. If Quad SPI mode is not activated, pull-up resistor to HOLD_L/IO3 is recommended. The HOLD_L pin has to be tied high to make sure HOLD function is not enabled unintentionally

Can narrow and standard package of SOP8 and WSON8 share the same package layout land pattern on PCB?

If the land pattern fingers can be designed with sufficient length, SOP8 150mil and 208mil packages can share the same package layout land pattern.

WSON8 6x5mm and 8x6mm packages can also share the same land pattern. In additional, the SOP8 and WSON8 can also share the same land pattern and are exchangeable.

In conclusion, customer can take the advantage to use the same PCB design for all four different Winbond 8 pins or 8 pads packages, if the land pattern is properly designed.

This can greatly reduce the PCB re-design effort and cost to accommodate different package’s needs for different platforms.

How to connect the center pad in SON packages?

The center pad is structural and not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. 

Program and/or Erase not working.

Make sure to send a Write Enable (06h) instruction before any program, erase instructions.

Write Protect pin (/WP) not working.

It is a common misconception that /WP pin is for protecting the flash memory content. /WP actually prevents writing to the status register. Protection control bits in the Status Register have to configured first and then use the /WP pin as a hardware control. Software control protection without /WP pin can also be used. Refer to the Write Protection section in the datasheet for more details.

How to enable single or dual SPI mode if Quad Enable bit (QE) is always enabled in Q suffix parts?

Quad Enabled bit (QE) is always enabled by default only meant quad mode is always available. It does not disable single or dual SPI modes. If a single or dual SPI instruction is sent, the flash will execute the instruction in single or dual mode accordingly.

What is Winbond flash's Moisture Sensitivity Level (MSL)?

All Winbond flash devices are MSL 3.

Do I have to perform a chip erase on fresh devices?

All Winbond flash are shipped in all erased state from the factory.

How do I know if erase has completed?

Poll the Status Register "BUSY bit". If BUSY becomes "0", it means the erase operation has completed.

I'm using a W74M12JV in my design but it has gone EOL. Is there a replacement part that I can use?

You can migrate to W25R128JV. The W74M and W25R family are the same and interchangeable. Winbond has migrated all W74M industrial applications to the W25R RPMC family.

What is the maximum reflow temperature?

You can request the reflow profile through Winbond's Technical Support link. https://www.winbond.com/hq/support/technical-support/?__locale=en

Some vendors support a separate VIO using pin14 in SOP16 package. What will happen if this VIO pin is connected to VCC in Winbond flash that do not support a separate VIO?

This VIO (SOP16 pin14) is not connected internally, there is no issue connecting VCC to this pin. 

Product selection
What is the difference between PSRAM and CRAM?

PSRAM is Pseudo-SRAM. CRAM is Cellular-RAM.  Actually, CRAM is the most popular PSRAM  for various applications in  industry.

What is the difference between LPDDR1 and LPDDR?

In JEDEC standard , the official naming is LPDDR (Low Power Double Data Rate).
Actually , LPDDR1 and LPDDR are the same .

What is the difference between Pseudo SRAM(CRAM) and Low Power DDR?

Pseudo SRAM  targets lower-density and lower throughput application, which is usually less than 128Mb and slower than 166MHz(Most cases are for 133 MHz). Otherwise, you could consider Low Power DDR.   

What is the difference between Mobile and Specialty DRAM

Most difference between Mobile and Specialty DRAM is that Mobile dram emphasizes power saving property, particularly in standby mode. If your product is powerlizeded by cell, we will suggest mobile dram is prefered.

What is the different between DDR3 & DDR3L

DDR3 is operating at VDD = VDDQ = 1.5V ± 0.075V
DDR3L is operating at Power supply = 1.35V (typ.) VDD = VDDQ = 1.283V to 1.45V. Winbond DDR3L is backward compatible to VDD = VDDQ = 1.5V ± 0.075V.

NOR Flash
What are some of the nor products you offer?

We offer Serial NOR Flash from 512Mb through 512Gb densities. We also have a complimentary Parallel NOR Flash GL family of products ranging from 32Mb through 512Mb densities.

What is your Serial NOR Flash offering?

Winbond is the leader in Serial NOR Flash both in units and in revenue. We offer Serial flash from 512Mb through 512Gb densities. These products are available in standard/dual and Quad SPI, as well as QPI mode for higher performance, at the same price and offer the flexibility to customers to use these products to suit their applications.

What is the advantage of your Parallel NOR Flash offering?

Our Parallel NOR Flash GL family of products ranging from 32Mb through 256Mb densities are industry standard compatible. Customers using our products can plug and play since they do not have to make any firmware or software changes to their existing designs.

What are some features of the Serial NOR Flash family?

Quad SPI power-up and SFDP (Serial Flash Discoverable Parameters)  are Intel PC requirements that we offer. Fast write, Program/Erase Suspend/Resume, Burst with Wrap, Volatile status register write, complement array protection are features supporting mobile telephone and other applications. In addtion to this, for enhanced security, we offer OTP array and registers, software and hardware reset, programmable output drive and independent block lock features.

What are some new families of Serial Flash products?

The W25CL family of low density products ranging from 1Mb through 4Mb replace the older generation 3V and 2.5V families, and these are available in production now. The EW 1.8V family from 1Mb through 8Mb densities is available in production now. The JV family of 3V products from 16Mb through 512Mb and the JW 1.8V family of products from 16Mb through 512Mb are also available now.

What are the packaging options for Serial Flash products?

The popular Serial Flash products are offered in many different small packages . 208mil SOIC8 is the highest volume package and hence very cost effective. This is followed by the 150Mil SOIC package. For small form factor applications, the most popular package is the 6x5mm WSON8 followed by the 2x3mm USON8 package. Products in the 8x6mm BGA is for secure applications like the STB where the pins cannot be probed, and large density parts like the 256Mb or 512Mb are offered in the 8x6mm WSON or 300mil SOIC8 packages. For space constrained applications, packages like the WLCSP are popular, which are the smallest packages in the industry and we ofer KGD (Known Good Die) as well.

NAND Flash
What is the read performance difference between ONFI NAND and Serial NAND?

In the ideal condition, the Quad mode read performance of Serial NAND  is almost the same as ONFI NAND in byte mode.  Besides, Winbond Serial NAND supports the "Continuous Read Mode", which has double data transfer rate than ONFI NAND.  So, the Serial NAND read performance is better than ONFI NAND.

What are some of the product areas you have newly developed?

We have developed a new family of products in the NAND area. Our NOR flash offering goes up to 512Mb and beyond this density, we will migrate to SLC NAND where we have developed products in the 1Gb, 2Gb, 4Gb and 8Gb densities. The Serial NAND products will be an extension of the NOR products with the same SPI interface. The primary focus of these products is to store code. Many of these products are used to store data in addition to code depending on the application.

What is the difference between NAND Flash and NOR Flash?

NAND Flash is more cost effective compared to NOR flash at 512Mb densities and higher. NAND flash at higher densities (512Mb and above) is typically used for data storage. NOR Flash is commonly used from 512Kb through 512Mb densities for code storage.

Spec question/ product feature
How could I decide the speed, I/O pins or package type of DRAM device?

The choice of DRAM type will depend on computing bandwidth of all IP in SOC. You need to figure out how much all IPs total computing needs(Usually video application occupy most bandwidth). Once deciding, you could choose 32 or 16 IO(usually) and how fast working frequency you use to achieve required throughput. Package type of DRAM is also usually subject to customer’s application. KGD or Package(how many balls) is most common. 

Why DLL is not used LPDDR/ LPDDR2 ?

For conventional DDR , DLL (Delay Lock Loop) is typically used . For LPDDR,DLL is not necessary and beneficial for  power saving.

What is the speed difference between LPDDR1 and LPDDR2?

For speed, LPDDR2 affords  533MHz  and LPDDR affords  200MHz.

NAND Flash
What is ONFI?

The Open NAND Flash Interface (ONFI) is an industry Workgroup made up of more than 100 companies that build, design-in, or enable NAND Flash memory. It is dedicated to simplifying NAND Flash integration into consumer electronic products, computing platforms, and any other application that requires solid state mass storage. It defines standardized component-level interface specifications as well as connector and module form factor specifications for NAND Flash.

What is MLC and SLC?

The SLC means Single-Level Cell and the one unit of SLC only can store 1bit information (0/1). The MLC means Multi-Level Cell. The MLC unit can store 2bits information (00/01/10/11). Therefore, MLC Flash devices cost
less and allow for higher storage density. SLC Flash devices provide better performance and greater reliability.

What is bad block?

An bad block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC.  Block 0, block address 00h is guaranteed to be a valid block at the time of shipment. Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All initial invalid blocks are marked with non-FFh at the first byte of spare area on the 1st or 2nd page.

What is spare area in NAND?

Each page consists of the main data storage area and the spare data area. Typically, the main area is used for user data or code storage and the spare area is used for error management functions.

Does Winbond have permanent lock (Secured) NAND?

Yes, Winbond has permanent lock (Secured) NAND.  Please contact Winbond sales force or agent to get the product ordering informaiton.

Technical issue
What should I pay attention to if I want to replacement DRAM from other vender?

First, we should confirm both density are same or not. Then follow the datasheet specification, Every vendor’s data output time may a little bit different, we suggest customer to fine tune data latch time in SoC configuration after replacing different vendor DRAM.

Specialty DRAM
How do we judge the DQ is read or write by waveform point view ?

The waveform relation between DQ read and DQS is edge-aligned.                                                                                                                 The waveform relation between DQ write and DQS is center-aligned.

Whether if the 2Gb DDR3 DRAM can used as drop in replacement in the same layout as 1Gbit DDR3 DRAM?

If you already reserve A13 in PCB layout and the controller support 2Gb DDR3 DRAM also, you can replacement 1Gb DDR3 DRAM by 2Gb DDR3 DRAM. And please modify row/column address as 2Gb datasheet definition by software setting.

Mobile DRAM
How to handle the clock in asynchronous mode?

In asynchronous  mode, the clock should be fixed low.

What are the different applications of LPDDR and DDR?

LPDDR with power saving features is mainly used for mobile applications, like mobile phone .
Generally, mobile application is battery-based and power consumption is a key concern.
Conventional DDR is mainly for ordinary applications.

What are the different applications of LPDDR2 and DDR2 ?

LPDDR2 with power saving features  is mainly used for mobile  applications, like mobile phone  .  Generally, mobile application is battery-based and power consumption is a key concern.  Conventional  DDR2 is mainly for  ordinary applications.

NAND Flash
Can host use 4bit ECC algorithm in 1bit ECC NAND?

Yes, the 1bit ECC NAND means the NAND Flash only has 1 error bit in normal operation.  In general, the NAND Flash spare area is 64Byte at least.  The 64Byte is big enough to put 4bit ECC parity and META data from file system. So, host can use 4bit ECC algorithm and put the 4bit ECC parity the 64Byte spare area of the 1bit ECC NAND.

Can Winbond Serial NAND be accessed by legacy SPI controller?

Yes, Winbond Seiral NAND provides the continuous read mode, which can backward compatible with major read commands used by SPI-NOR.  The legacy platform can read out the boot code from Serial NAND in this mode to bring up the system.

How can we get Winbond DRAM SPD code?

Usually, SPD code is used for DRAM module, if you need our SPD file, please provide your SPD file to us, we can help to Modify SPD code for Winbond.

Where could I get power consumption, board layout information of  product?

Please seek to our FAE’s help. We dedicate to statisfy customer’s need.

What information Winbond will provide, if you decide to kick off project?

Winbond has much experience in helping customer completing through whole project. Our territory account will help you estimate your need and advise you a best solution when you inquiry. Please don’t hesitate to contact us if you need.

NAND Flash
What is the advantage of the Serial NAND (Winbond's products)?

First, Winbond serial NAND can provide the 52MB/s data transfer rate to improve the system performance. Second, the PCB layout and size are reduced due to 8pin small WSON package. Third, the SoC also can simplify the memory interface and reduce the pin count by removing traditional parallel NAND interface.  Overall, the system performance is improved and the sytem BOM cost is reduced.

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