W9712G6KB
The W9712G6KB is a 128M bits DDR2 SDRAM and speed involving -25, 25I and -3
製品の特色
Double Data Rate architecture: two data transfers per clock cycleCAS Latency: 3, 4, 5 and 6
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Package
TFBGA 84
Specifications
Part No. | W9712G6KB | Voltage | 1.8V±0.1V |
---|---|---|---|
Speed | 333 / 400 MHz | Temp. | C-temp, I-temp/ Automotive |
Organization | 8Mbitx16 | Automotive | P |
Status | P |